low-power min/max architecture in 32nm cntfet technology for fuzzy applications based on a novel comparator

In this paper, the design of a novel low-power min/max circuit using carbon nanotube field-effect transistor (cntfet) technology has been discussed. by employing a new structure for the implementation of digital comparator, a high performance configuration has been obtained which consumes small area on chip due to the low transistor count used for its implementation. because the comparator is capable of comparing 4-bit words, the designed circuitry can also be expanded to operate as a winner-takes-all (wta) or loser- takes-all (lta) system. the circuit is first simulated in a complementary metal-oxide-semiconductor (cmos) process to demonstrate its correct performance and then, the simulations have been performed for the cntfet technology to indicate that the design procedure is independent of the employed technology. in order to show the advantages of the proposed circuitry in a better manner, the state-of-the-art similar works have been redesignated and simulated along with our work. based on the simulation results for cntfet 32 nm standard process, the proposed comparator consumes 8.3μw from 0.9v power supply, while its total transistor count is 66.