conventional vs. junctionless gate-stack dg-mosfet based cmos inverter

In this article, the high-k gate dielectric effect on the operation of complementary metal oxide semiconductor (cmos) inverter build using conventional (cl) double-gate (dg) metal oxide semiconductor field effect transistor (mosfet) and junctionless (jl) double-gate (dg) mosfet has been explored. it is found that the improvement in inverter performance is more pronounced in cl-dg-mosfet based cmos inverter in comparison to jl-dg-mosfet based cmos inverter when sio2 is replaced by the high-k dielectric at gate oxide. the improvement in low noise margin (δnml), high noise margin (δnmh), gain (δa) & propagation delay (δpd) is 3.19%, 1.64%, 5.2% & 0.9% respectively when sio2 is replaced by tio2 at gate oxide in case of cl-dg-mosfet based cmos inverter whereas it is 1.96%, 1.24%, 3.4% & 1.71% respectively in case of jldg-mosfet based cmos inverter. consequently, the utilization of high-k dielectric as gate oxide is more advantageous in cl-dg-mosfet devices for improved stability and gain of cmos inverter.