channel thickness dependency of highk gate dielectric based double-gate cmos inverter

This work investigates the channel thickness dependency of high-k gate dielectric-based complementarymetal-oxide-semiconductor (cmos) inverter circuit built using a conventional double-gate metal gate oxidesemiconductor field-effect transistor (dg-mosfet). it is espied that the use of high-k dielectric as a gateoxide in n/p dg-mosfet based cmos inverter results in a high noise margin as well as gain. it is alsofound that delay performance of the inverter circuit also gets upgraded slightly by using high-k gate dielectricmaterials. further, it is observed that the scaling down of channel thickness (t_si) improves the noise margin(nm), and gain (a) at the cost of propagation delay (pd). moreover, it is also observed that the changes innoise margin (δnm = nm_(k=40) – nm_(k=3.9)), propagation delay (δp_d = p_d (k=40) – p_d (k=3.9)), and gain (δa =a_(k=40) – a_(k=3.9)) gets hinder at lower t_si. therefore, it is apposite to look at lower channel thickness (~6 nm)while designing high-k gate dielectric-based dg-mosfet for cmos inverter cell.