high speed radix4 booth scheme in cntfet technology for high performance parallel multipliers

A novel and robust scheme for radix-4 booth scheme implemented in carbon nanotube field-effect transistor (cntfet) technology has been presented in this paper. the main advantage of the proposed scheme is its improved speed perfor-mance compared with previous designs. with the help of modifications applied to the encoder section using pass transistor logic (ptl), the corresponding capacitances of middle stages have been reduced considerably. as a result, total transistor count along with power consumption has been decreased illustrating the other advantages of the designed structure. for evaluation of correct functionality, simulations using cntfet 32nm standard process have been performed for the de-signed scheme which depict the latency of 195ps for critical path. meanwhile, comparison with previous works using the power delay product (pdp) criteria demonstrates the superiority of the proposed structure suggesting that our circuitry can be widely utilized for high speed parallel multiplier design.