design of a low power high speed 4-2 compressor using cntfet 32nm technology for parallel multipliers

In this article a low power and low latency 4-2 compressor has been presented. by using modified truth table and pass transistor logic (ptl) a novel structure has been proposed which outperforms previous designs from the frequency of operation view point. the proposed design method has reduced the total transistor count considerably which will lead to reduced power consumption and smaller active area in the final realized circuit. comparison with previous works depicts that the proposed structure has the lowest number of transistor among them. the proposed design has been designed and simulated in carbon nanotube field-effect transistor (cntfet) technology having 32nm channel dimension. the comparison with the best reported recent designs demonstrates the superiority of the proposed work; these reported designs in literature were simulated here in the same settings and process to perform a fair comparison. in addition, the complementary metal-oxide-semiconductor (cmos) 32nm standard process has also been employed to realize the proposed circuit and to do the comparison between cmos and cntfet technologies which illustrates the advantage of cntfet over standard cmos processes. the transistor level delay for the critical path of the proposed design is equal to 4 transistors which is equal to the best reported work in the literature; however, in the proposed work here the total number of transistors is reduced to 58 which according to the authors knowledge is the lowest numb reported for a 4-2 compressor block in the papers.