Evaluation of inverter reliability performance due to negative bias temperature instability (NBTI) effects in advance CMOS technology nodes

Negative bias temperature instability (nbti) is the most concern issue cmos devices with the scaling down of the cmos technologies. nbti effect contributes to p-mosfet device degradation which later reduce the performance and reliability of cmos circuits. this paper presents a reliability simulation study based on r-d model on cmos inverter circuit. hspice mosra model together with the predictive technology model (ptm) was used as to incorporate the nbti model in the circuit reliability simulation study for different technology nodes. ptm of high performance (hp) models of 16nm,22nm,32nm and 45nm were used in this simulation study. the atomic hydrogen based model was integrated in the simulation. the results show that in a cmos inverter circuit,the threshold voltage shift of p-mosfet under nbti stressing increased as the year progressed.. the threshold voltage shift was observed to increase up to 45.1% after 10 years of operation. the time exponent,n ~ 0.232 of the threshold voltage shift observed indicates that the defect mechanism contributed to the degradation is atomic hydrogen. the propagation delay increased to 19.5% over a 10-year period. s up to 19.5% from the zero year of operation until 10 years of the operation. in addition,the time propagation delay increased as year increased when the technology nodes smaller. the finding is important for understanding reliability issues related to advanced technology nodes in cmos circuits study. © 2017 universiti putra malaysia press.