High Performance Low Latency 16×16 Bit Booth Multiplier Using Novel 4-2 Compressor Structure

In this article, the design procedure of a low latency booth multiplier has been proposed. with the help of a novel 4-2 compressor, a high-performance 16×16 bit booth multiplier has been implemented, which depicts high operating frequency. to achieve this, the proposed 4-2 compressor has been utilized successively in the partial product reduction tree (pprt) of the multiplier and by means of radix-4 booth scheme, the multiplier has been designed. the partial product (pp) generation circuitry is also based on the other work published by the authors which enables the designed structure to work at the frequency of 350mhz. the main advantage of the designed compressor is the elimination of the middle stage inverters between cascaded blocks of pprt which considerably enhances the speed of whole system. simulation results for tsmc 0.18μm cmos technology and 1.8v power supply have been demonstrated to confirm the correct operation of proposed 4-2 compressor. according to the results, the achieved delay of the critical path for hard test and high capacitive load, equal to 100ff, is 936ps while a power consumption of 255.15μw has been achieved at the operating frequency of 100mhz.