reducing the power consumption in flash adc using 65nm cmos technology

Today, given the extensive use of convertors in industry, reducing the power consumed by theseconvertors is of great importance. this study presents a new method to reduce consumption power in flashadc in 65nm cmos technology. the simulation results indicate a considerable decrease in powerconsumption, using the proposed method. the simulations used a frequency of 1 ghz, resulting in decreasedpower consumption by approximately 90% for different processing corners. in addition, in this paper theproposed method is designed using an interpolation technique for the purpose of promoting the performanceas well as decreasing the class of chip. the simulation results indicate that the power consumption for theinterpolation technique is decreased by approximately 5% compared to the proposed method. on the otherhand, we compare the results of the proposed convector with those of convertors frequently referred in otherstudies. also, the results show that the power consumption is considerably decreased, using the proposedmethod.