a cmos 3.5 ghz bandwidth low noise amplifier using active inductor

This paper presents a 3.5 ghz bandwidth wideband low noise amplifier (lna) with low power consumption, high power gain, and acceptable linearity in 130 nm cmos technology for use as a separate chip. the lna includes two parallel branches: a gm-boosted common-gate (cg) path and a common-source (cs) current reuse path. the cg path handles wideband input impedance matching, while the cs path is utilized to achieve enough power gain and enhance linearity. the noise cancellation technique is adopted to reduce the noise generated by the gm-boosted cg stage, and linearity is taken care of by choosing suitable gain values for cg and cs. also, an active inductive shunt-peaking technique is used to increase the bandwidth to 3.5 ghz. the post-layout simulation results of the circuit in 130 nm cmos technology show that in the whole bandwidth of 0.25 ghz to 3.75 ghz the power gain, noise figure, and third-order input intercept point (iip3) are 15±1 db, 2.25±0.3 db, and -5.5 dbm, respectively. also, the s11 and s22 are less than -15 db and -19 db, which is adequate for an lna integrated circuit. the proposed lna consumes 4.7 mw with a 1 v power supply and occupies an area of 0.047 mm2.