cntfet based pseudo ternary adder design and simulation

Utilizing multiple logic instead of binary logic levels makes the same system to be realized with reduced number of internal connections and wiring, and occupying smaller chip area while achieving higher operational speed. in spite of all the mentioned advantages, the multilevel logic systems relay on voltage dividing mechanism to provide suitable mid-voltage outputs. however, this requires a direct current flow from supply voltage to the ground, making the structure power hungry. eliminating the mid-voltage outputs can help the structure to resemble binary design approach and be more power efficient, as will be discussed. in this paper, pseudo ternary addition blocks, namely a half-adder, a full-adder block are designed and implemented based on cntfet, which try to eliminate 1 output for mid-stages wherever possible. the proposed adders are implemented, simulated and verified in hspice software using 32nm cntfet technology. the simulation results reveal the proposed pseudo ternary full-adder block consumes just 1.037 mw power and has the propagation delay of 290 ps.