a broadband low power cmos lna for 3.1–10.6 ghz uwb receivers

A new approach for designing an ultra wideband (uwb) cmos low noise amplifier (lna) is presented. the aim of this design is to achieve a low noise figure, reasonable power gain and low power consumption in 3.110.6 ghz. also, the figure of merit (fom) is significantly improved at 180nm technology compared to the other stateoftheart designs. improved pi;network and tnetwork are used to obtain a high and smooth power gain for the whole frequency band. impedance matching and noise matching are designed with double feedback and only one inductor that are used at the input of the lna. post layout simulation is done for design validation. in this design post layout simulations show the low noise figure of 3.85 plusmn;0.25 db, reasonable power gain (18.08db) and input return loss less than 9.1db in full band of uwb. the power consumption of the circuit is only 11.3mw from 1.8v voltage supply. the lna has the group delay about 111 plusmn;43ps. an input thirdorder intermodulation point (iip3) of 9.2 dbm is achieved at 4 ghz. the layout area is 1.056 times; 0.658 mm2.